Impact of Leakage Power Reduction Techniques on Parametric Yield

Low-Power Design of Digital Integrated Circuits under Process Parameter Variations
by Sudip Roy - Sold by Dodax EU
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Sudip Roy Impact of Leakage Power Reduction Techniques on Parametric Yield
Sudip Roy - Impact of Leakage Power Reduction Techniques on Parametric Yield

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With the advancement of process technology for fabrication of integrated circuits, the magnitude of variations in process parameters have increased and the parametric yield loss problem has become a serious concern of the fabrication houses. Thus, the traditional techniques for power and delay optimization in design automation tools can no longer be used effectively. This has opened up a challenge to the chip designers to design integrated circuits, which are variation tolerant and thereby having higher parametric yield. In this monograph, a single threshold voltage based approach is proposed that exhibits runtime leakage power reduction comparable to the existing dual threshold voltage assignment approaches and at the same time the proposed approach is less sensitive to process parameter variations. Again, this logic-level runtime leakage reduction technique is combined with multiple supply voltage assignment during high-level synthesis for total power reduction. It is believed that the proposed leakage power reduction technique will be useful in digital circuit design flow (logic-level and high-level syntheses) under process parameter variation.


Author Sudip Roy

Author Ajit Pal

Product Details


GTIN 9783659273919

Pages 172

Product type Paperback

Dimension 8.66 x 5.91 x 0.35  inches

Product Weight 8.64 ounces

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